1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory and, more particularly, to an electrically erasable and programmable semiconductor nonvolatile memory, e.g., EEPROM (Electrically Erasable and Programmable Read Only Memory). On the other hand, the invention relates to a semiconductor device which is constructed of thin film transistors (as will be called the “TFT”) formed by the SOI (Silicon On Insulator) technique. Especially, the invention relates to a semiconductor device in which a semiconductor nonvolatile memory, a pixel portion and a drive circuit for the pixel portion are integrally formed over a substrate having an insulating surface.
Herein, the electrically erasable and programmable read only memory (EEPROM) literally indicates all the electrically erasable and programmable semiconductor nonvolatile memories and contains a full-function EEPROM and a flash memory, for example, under its category. On the other hand, the nonvolatile memory and the semiconductor nonvolatile memory will be used to have the same meaning as that of the EEPROM, unless otherwise specified. Herein, moreover, the semiconductor device indicates all the devices for functioning by utilizing the semiconductor characteristics and contains an electrooptic device represented by a liquid crystal display device or an EL display device, and an electronic device having the electrooptic device mounted thereon, under its category.
2. Description of Related Art
In recent years, there has rapidly spread a small-sized semiconductor device of multiple high functions, as represented by a mobile device such as a mobile computer or a mobile telephone. Accordingly, a semiconductor nonvolatile memory has been noted as a memory composing the semiconductor device. This semiconductor nonvolatile memory is characteristically inferior in the storage capacity but superior in the integration density, the shock resistance, the power consumption and the writing/reading speeds, to a magnetic disk. In recent years, there has been developed a semiconductor nonvolatile memory which has sufficient performances of the number of rewriting operations and the time period for holding the data by solving its intrinsic problems. There has been a trend to employ the semiconductor nonvolatile memory in place of the magnetic disk.
The semiconductor nonvolatile memory is coarsely divided into two classes: the full-function EEPROM and the flash memory. The full-function EEPROM is a semiconductor nonvolatile memory capable of erasing at each 1 bit so that it can perform all the writing, reading and erasing operations at each 1 bit. The EEPROM has higher functions than those of the flash memory but is inferior thereto in the integration degree and the cost. On the other hand, the flash memory is a semiconductor nonvolatile memory for erasing the memory in a batch or at the block unit so that it realizes a high integration density and a low cost while sacrificing the erasure at each 1 bit.
Here is taken up the full-function EEPROM having higher functions as the semiconductor nonvolatile memory of the prior art, to describe the circuit diagram, and the sectional diagram and the driving method of a memory cell.
FIG. 4 is a circuit diagram of the full-function EEPROM of the prior art. In FIG. 4, the full-function EEPROM is constructed to include: a memory cell array 405 having a plurality of memory cells (1, 1) to (n, m) arranged in a matrix shape of an m-number of columns× an n-number of rows; an X-address decoder 401; a Y-address decoder 402; and other peripheral circuits (drive circuits) 403 and 404. The other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier and a booster circuit, which are provided, if necessary.
Each memory cell (as represented by a memory cell (i, j) (i: an integer of 1 or more and n or less, and j: an integer of 1 or more and m or less)) has an n-channel memory transistor Tr1 and an n-channel selection transistor Tr2, which are connected in series. Moreover, the memory transistor Tr1 is connected at its source electrode and control gate electrode with a source line Si and a word line Wj, respectively. The selection transistor Tr2 is connected at its drain electrode and gate electrode with a bit line Bi and a selection line Vj, respectively. On the other hand, bit lines B1 to Bn are connected with the Y-address decoder 402, and word lines W1 to Wm and selection lines V1 to Vm are individually connected with the X-address decoder 401. All source lines S1 to Sn are commonly fed with a predetermined potential Vs.
Where the memory transistors owned by each memory cell are to record data of 1 bit, the full-function EEPROM, as shown in FIG. 4, has a storage capacity of m×n bits.
The data are written, read and erased in one memory cell selected by the X-address decoder 401 and the Y-address decoder 402. Here will be described the writing, reading and erasing operations by taking the memory cell (1, 1) as an example. Here in the specification, the writing operation is to inject electrons into the floating gate electrode of the memory transistor, and the erasing operation is to release the electrons from the floating gate electrode. As a result, the writing operation raises the threshold voltage of the memory transistor, and the erasing operation lowers the threshold voltage.
First of all, where the data are written in the memory transistor Tr1, the source lines S1 to Sn are dropped to a level GND, and a positive high voltage (e.g., 20 V) is applied individually to the bit line B1 and the word line W1. On the other hand, a positive voltage (e.g., 20 V) to turn ON the selection transistor Tr2 is applied to the selection line V1. Under this condition, a high electric field is established to cause an impact ionization in the vicinity of the drain of the memory transistor Tr1. Since the high electric field is also established in the gate direction, moreover, the hot electrons generated are injected into the floating gate electrode so that the writing is effected. The threshold voltage of the memory transistor Tr1 changes depending upon the charge which is stored in the floating gate electrode.
Where the data are to be read from the memory transistor Tr1, the source lines S1 to Sn are dropped to the level GND, and a predetermined voltage (as will be described hereinafter) is applied to the word line W1. On the other hand, a voltage (e.g., 5 V) to turn ON the selection transistor is applied to the selection line V1. According to the threshold voltages of the cases in which the charge is stored and not in the floating gate electrode of the memory transistor Tr1, the data stored in the memory cell are read from the bit line B1.
Here, the predetermined voltage may be set between the threshold voltage in the erased state (in which the electrons are not stored in the floating gate electrode) and the threshold voltage in the written state (in which the electrons are stored in the floating gate electrode). Where the memory transistor in the erased state has a threshold voltage of 2 V or lower and where the memory transistor in the written state has a threshold voltage of 4 V or higher, for example, the predetermined voltage can be exemplified by 3 V.
Where the data stored in the memory transistor Tr1 are to be erased, the source line S1 and the word line W1 are dropped to the level GND, and a positive high voltage (e.g., 20 V) is applied to the bit line B1. On the other hand, a positive high voltage (e.g., 20 V) is applied to the selection line V1 to turn ON the selection transistor Tr2. At this time, a high potential difference is established between the gate-drain of the memory transistor Tr1 so that the electrons stored in the floating gate electrode are released through the tunnel current to the drain region thereby to effect the erasure.
Here, it is assumed that all the signal lines B2 to Bn and W2 to Wm unselected at the writing, reading and erasing times are at 0 V. On the other hand, the above-specified values of the operating voltages are just examples and should not be limited thereto.
For the operations at each 1 bit, when the selected memory cell (1, 1) is written, read and erased, the unselected memory cells (i.e., all the memory cells other than the memory cell (1, 1) in this case) should not be written, read or erased. As a matter of fact, in the memory cells other than the first row, the selection lines V2 to Vn are at 0 V so that the selection transistors are OFF, and the memory transistors are not written or erased while being uninfluenced by the reading time. In the memory cells other than those of the first column, on the other hand, no potential difference is established between the source lines—the bit lines so that the memory cells are not written while being uninfluenced by the reading time. Without the potential difference between the word lines—the bit lines, nor is effected the erasure.
As has been described hereinbefore, the selected memory cell (1, 1) is written, read and erased without causing the malfunctions of the unselected memory cells.
Finally, a representative sectional structure of the memory cells constructing the full-function EEPROM of the prior art is shown in FIG. 5. In FIG. 5, the memory transistor Tr1 (of the n-channel type) and the selection transistor Tr2 (of the n-channel type) are formed over a p-type silicon substrate 500. The memory transistor Tr1 is constructed to include: source/drain regions (or highly doped n-type impurity regions) 501 and 502 and a channel forming region 504 formed in the vicinity of the surface of the silicon substrate 500; and a first gate insulating film 506, a floating gate electrode 508, a second gate insulating film 510 and a control gate electrode 511. The selection transistor Tr2 is constructed to include: source/drain regions (of highly doped n-type impurity regions) 502 and 503 and a channel forming region 505; and a first gate insulating film 507 and a gate electrode 509. Over a layer film 512, on the other hand, there are lead a source wiring line 513 and a drain wiring line 514 through contact holes.
Here in FIG. 5, the drain region 502 and the floating gate electrode 508 of the memory transistor Tr1 overlap partially through the first gate insulating film 506. This overlap region is one for causing the tunnel current to flow in the erasing operation.
It has already been described that the semiconductor nonvolatile memory is divided into the full-function EEPROM and the flash memory. The full-Function EEPROM is a functionally excellent memory capable of acting for each 1 bit. In the full-function EEPROM, however, the memory cell for storing data of 1 bit is constructed of two transistors, i.e., the memory transistor and the selection transistor so that the EEPROM is troubled by a large memory cell area and a low integration density. These troubles obstruct the lower size and the lower cost of the full-function EEPROM.
The flash memory can be said such one mode of the semiconductor nonvolatile memory as can realize a high integration density. The memory cell constructing the flash memory is composed of one memory transistor so that it realizes a high integration density while sacrificing the erasing operation for each 1 bit. In the flash memory, all data have to be erased to rewrite the data of 1 bit. This makes the power consumption higher than that of the full-function EEPROM and lowers the reliability because the memory cells are rewritten although unnecessary. Of course, the flash memory cannot be used for an application requiring the erasure of 1 bit.